Bistable nematic liquid crystal display device and method for controlling such a device

ABSTRACT

The present invention relates to a display device comprising a bistable nematic liquid-crystal matrix screen with anchoring breaking, characterized in that it comprises:
         components ( 40 ) capable of switching between an off state and an on state, these components being placed respectively between a drive electrode ( 47 ) associated with each pixel and a display state control link ( 45 ); and   means capable of applying, to the input of each aforementioned component ( 40 ), via the state control link ( 45 ), input signals comprising at least two phases separated by a controlled time interval, namely a first phase during which the input signal has an amplitude sufficient to permit breaking of the anchoring of the liquid crystal on the associated pixel, then a second phase during which the amplitude of the input signal is controlled in order to select one of the two bistable states of the liquid crystal, the time interval between the two phases being adapted in order to break the anchoring of the liquid crystal on the said associated pixel before the second input signal phase is applied.

TECHNICAL FIELD

The present invention relates to the field of liquid-crystal displaydevices and more particularly to a method and a device for switching abistable nematic display.

OBJECT OF THE INVENTION

A general object of the present invention is to improve the bistabledisplay devices disclosed in document [1]. These devices are generallycalled “BiNem” devices. This terminology will be used for the purposesof the present patent application. The structure of these devices willbe described in greater detail below.

PRIOR ART

A distinction may be made between nematic devices, cholesteric devices,smectic devices, ferroelectric devices and other devices according tothe physical nature of the liquid crystal used. In nematic displays,which form the subject matter of the present invention, use is made ofan achiral nematic or a chiralized nematic (for example chiralized byadding a chiral dopant). What is obtained in this way is a spontaneoustexture that is uniform or slightly twisted, the pitch of the helix ofwhich is greater than a few microns. The orientation and the anchoringof the liquid crystal near the surfaces bounded by substrates aredefined by alignment layers or treatments applied to the saidsubstrates. In the absence of a field, a uniform or slightly twistednematic texture is imposed in this way.

Most devices proposed and produced hitherto are mono-stable. In theabsence of a field, only a single texture is produced in the device.This texture corresponds to an absolute minimum of the total energy ofthe cell. In a field, this texture is continuously deformed and itsoptical properties vary according to the voltage applied. When the fieldis removed, the nematic returns again to the single monostable texture.Those skilled in the art will recognize among these systems theoperating modes most widely employed in nematic displays: twistednematics (TN), super twisted nematics (STN), electrically controlledbirefringence (ECB) nematics, vertically aligned nematics (VAN),in-plane switching (IPS) nematics, etc.

Another class of nematic displays is that of bistable, multistable ormetastable nematics. In this case, at least two separate textures—thatare stable or metastable in the absence of a field—may be produced inthe cell. Switching between the two states is achieved by applyingsuitable electrical signals. Once the image has been written, it remainsstored in the absence of a field thanks to the bistability. This memoryof bistable displays is very attractive for many applications. Firstly,it makes it possible to achieve a low image refresh rate (only when itis desired to change it), very favourable for reducing the powerconsumption of portable equipment. Secondly, the memory makes itpossible to have a very high degree of multi-plexing, with image qualityindependent of the number of rows.

Description of the Bistable Screen Called BiNem (FIG. 1)

A novel bistable display is disclosed in document [1].

This display is shown amatically in FIG. 1.

It consists of a chiralized nematic liquid-crystal or cholestericliquid-crystal layer 10 between two plates or substrates 20, 30, atleast one of which is transparent. Two electrodes 22, 32 placedrespectively on the substrates 20, 30 are used to apply electrical drivesignals to the chiralized nematic liquid crystal 10 lying between them.Anchoring layers 24, 34 on the electrodes 22, 32 orient the molecules ofthe liquid crystal 10 in the desired directions. The anchoring 24 of themolecules on a master plate 20 is strong and slightly tilted, while onthe slave plate 30 it is weak and flat. The anchoring 24, 34 of themolecules 10 on these surfaces 22, 32 is monostable.

An optical system completes the device.

More precisely, FIG. 1 shows schematically, on the left and on the rightrespectively, two states, each stable in the absence of a field, whichcan be occupied by the liquid-crystal molecules and, illustrated in thecentre of the same FIG. 1 is a broken state that is stable in a highelectric field and unstable in the absence of a field. This state istemporarily occupied by the liquid-crystal molecules during the processof driving the display.

The two bistable textures—U (uniform or slightly twisted) and T(twisted)—of the liquid crystal, illustrated on the left and on theright in FIG. 1 respectively, are stable with no field applied. Theangle between the direction of anchoring on the master plate 20 and thaton the slave plate 30 is small or zero. The twists of the two texturesdiffer in absolute value by about 180°. The spontaneous pitch p₀ of thenematic is chosen to be close to 4 times the thickness d of the cell(p₀≅4.d) in order to make the energies of the U and T texturesessentially the same. With no field, there exists no other state with alower energy: U and T exhibit true bistability.

One advantage of the BiNem structure is that the two textures—U andT—are planar, thereby making it possible to obtain a good viewing anglewithout a compensation film. The optical performance characteristics ofthe BiNem in reflective configuration are described, for example, indocument [5].

Method of Switching Between the Textures of the BiNem

Switching from one texture to the other requires breaking the anchoringon the surface 32/34, possessing a low zenithal anchoring energy.

Physical Principle

The two bistable textures U and T are topologically separate—it isimpossible to transform one into the other by a continuous volumedistortion. The transformation from one U texture into a T texture, orvice versa, therefore requires either the anchoring on the surfaces tobe broken, induced by a strong external field, or the displacement of adisclination line. This second phenomenon, which is markedly slower thanthe first, may be disregarded and will not be explained in detail below.

Any alignment layer of a liquid crystal may be characterized by azenithal anchoring energy A_(z). This energy is always finite. It may beshown that there is therefore a likewise finite threshold field E_(c)(anchoring-breaking threshold), which gives the surface a homeotropictexture (H) whatever the previous no-field texture.

To break the anchoring requires the application of a field at leastequal to the threshold field E_(c). This field must be applied for along enough time for the reorientation of the liquid crystal near thesurface to result in the homeotropic texture as shown schematically inthe centre of FIG. 1. This minimum time depends on the amplitude of theapplied field, but also on the physical characteristics of the liquidcrystal and on the alignment layer.

In the static case (fields applied for a few milliseconds or more),E_(c)≅A_(z)/√{square root over (K₃₃ε₀Δε)}, where A_(z) is the zenithalanchoring energy of the surface, K₃₃ is the elastic bending coefficientof the liquid crystal, Δε is its relative dielectric anisotropy and ε₀is the dielectric constant of free space.

V_(c) is defined as the anchoring-breaking voltage such thatV_(c)=E_(c)·d, where d is the thickness of the liquid-crystal cell. Atypical value of V_(c) is 16 V in the case of a BiNem.

The anchoring is said to be broken when the molecules are normal to theplate near this surface and when the restoring torque exerted by thesurface on these molecules is zero. In practice, all that is required isfor the difference between the orientation of the molecules and thenormal to the surface to be small enough, for example less than 0.5°,and for the torque applied to the molecules at the surface to be quitesmall (such a state is shown schematically in the centre of FIG. 1).When these conditions are combined, the nematic molecules near thebroken surface 34 are in unstable equilibrium when the electric field isswitched off, and may either resume their initial orientation or rotatein the opposite direction and induce a new texture differing from theinitial texture by a 180° twist.

Control of the final texture depends on the waveform of the appliedelectrical signal, in particular on the way in which this field isreturned to zero.

A progressive reduction in the voltage of the pulse minimizes flow. Themolecules close to the master plate 20 slowly drop down to theirequilibrium state. Their elastic coupling with the molecules of thecentre of the specimen makes them also tilt in the same direction. Thismovement diffuses until reaching the slave plate 30 where the moleculesare in turn tilted rapidly in the same direction, aided by the surfacetorque. The uniform state U is progressively built up at the centre ofthe cell as shown schematically on the left of FIG. 1.

When the field suddenly decreases, the orientation of the liquid crystalis modified firstly near the strong surface (master plate 20), with asurface relaxation time of γ₁L²/K, where L=K₃₃/A_(z) is theextrapolation length of the strong layer and γ₁ is the rotationviscosity of the liquid crystal. This time is typically of the order often microseconds or so.

Switching the strong surface 24 in such a short time induces a strongflow close to this surface, which diffuses into the volume and reachesthe weak surface (slave plate 30) after a characteristic time of lessthan one microsecond. The shear induced on the weak surface (slave plate30) creates a hydrodynamic torque on the molecules at this surface. Thistorque is in the opposite direction to the elastic torque induced by thetilt of the master plate 20. When the shear is high enough, thehydrodynamic torque on the weak surface 34 is the strongest, promotingthe twisted texture T shown schematically on the right in FIG. 1. Whenthe shear is weaker, the elastic torque on the weak surface 34 is thestrongest, inducing the uniform texture U shown schematically on theleft in FIG. 1.

The direction of rotation of the molecules in the cell is indicated bytwo arrows referenced respectively as RU (for switching into the Ustate) and RT (for switching into the T state) in FIG. 1.

The volume then reorients, with a characteristic volume relaxation timeτ_(vol) of γ₁d²/K, where d is the thickness of the cell. This time,typically of the order of one millisecond, is much longer than therelaxation time of the strong surface.

Practical Implementation

In general, the switching of a BiNem-type liquid-crystal pixel takesplace in two phases (an anchoring-breaking first phase and a selectionsecond phase):

-   -   First phase: anchoring-breaking phase, denoted by C

The phase C consists in applying an electrical signal suitable forbreaking the anchoring on the slave plate 30. In general, the shorterthe phase C, the greater the peak amplitude of the applied signal mustbe.

For a given amplitude and a given duration, the details of the waveformof this signal (slopes, intermediate levels, etc.) do not have apronounced effect on the execution of the next phase, provided that theanchoring breaking has been carried out.

-   -   Second phase: selection phase, denoted by S

The voltage applied during the phase S must allow one of the twobistable textures—U or T—to be selected. On account of the effectexplained above, it is the falling waveform of the electrical pulseapplied to the terminals of each pixel that determines the switchingfrom one texture to the other.

To Switch to the Texture T:

Phase C: Anchoring Breaking

It is necessary, during the anchoring-breaking phase C to apply a pulsedelivering a field greater than the field for breaking the anchoring onthe slave plate 30 and to wait for the time required to lift themolecules in the pixel as illustrated in the centre of FIG. 1. Thebreaking field depends on the elastic and electrical properties of theliquid-crystal material 10 and on its interaction with the anchoringlayer 34 deposited on the slave plate 30 of the cell. It varies from afew volts to about ten volts per micron. The time to lift the moleculesis, proportional to the rotational viscosity γ and inverselyproportional to the dielectric anisotropy of the material 10 used and tothe square of the applied field. In practice, this time may come down toa few microseconds for fields of 20 volts per micron.

Phase S: Selection of the Texture

The field then merely has to be reduced rapidly, by creating over a fewmicroseconds, or at most a few tens of microseconds, a sudden drop inthe drive voltage. This sudden voltage drop, of amplitude at least equalto a value ΔV, is such that it is capable of inducing a sufficientlyintense hydrodynamic effect in the liquid crystal. To produce the Ttexture, this drop ΔV must necessarily take the applied voltage from avalue greater than the anchoring-breaking voltage V_(c) to a value belowthis voltage.

An example of a signal for switching to the T texture is a signal of thesquare-wave type, with an amplitude P1>V_(c) and P1≧ΔV. Its durationmust be long enough to break the anchoring. The drop from P1 to 0, withP1≧ΔV, allows T to be selected (cf. FIG. 2).

Another example of a signal for switching to the T texture is atwo-level signal comprising an anchoring-breaking first sequence ofduration τ₁ and amplitude P1, where P1>V_(c), followed by a selectionsecond sequence of duration τ₂ and amplitude P2 such that P2≧ΔV, i.e.P1−P2≧ΔV. The drop time of the applied field must be less than one tenthof its duration or less than 30 micro seconds in the case of long pulses(greater than 1 ms).

To Obtain the U Texture:

Phase C: Anchoring Breaking

It is necessary, during the anchoring-breaking phase C, to apply a fieldgreater than the anchoring-breaking field on the slave plate 30 for atime sufficient to lift the molecules as in the case of writing in theaforementioned state T.

Phase S: Texture Selection

It is then necessary to induce a “slow fall” in the voltage applied.Document [1] proposes two ways of implementing this “slow fall”: thesignal is either a pulse of duration τ₁ and amplitude P1 followed by aramp of duration τ₂, the fall time of which is greater than three timesthe duration of the pulse (FIG. 3), or a stepped fall.

An example of a signal for switching to the U texture is a two-levelsignal comprising a breaking first sequence of duration τ₁ and amplitudeP1 (P1>V_(c)) followed by a selection second sequence of duration τ₂ andamplitude P2 such that P2<ΔV and P1−P2<ΔV. The two-level stepped fall ismore easily achievable by means of digital electronics. However, it ispossible, of course, to imagine a fall in a larger number of levels thantwo.

It is thus possible, by applying a simple two-level signal to theterminals of the pixel to obtain either the U texture or the T texture.The first level (P1, τ₁) corresponds to the anchoring-breaking phase andthe second level (P2, τ₂) allows selection of the texture by the valueof P2. This signal is illustrated in FIG. 4. A P2T value corresponds toa value of P2 for switching to T (for a given P1) and a P2U valuecorresponds to a value of P2 for switching to a U texture (for a givenP1).

Typical values: P1=20 V, P2U=7 to 9 V for τ₁=τ₂=1 ms.

Conventional Addressing of the BiNem by Multiplexing

Principle of Conventional Multiplexing and Limitations

In the case of a medium-resolution matrix screen, a person skilled inthe art knows that it is out of the question to connect each pixelindividually to an independent drive electrode, as this would requireone connection per pixel, which is topologically impossible as soon asthe screen becomes complex. It is possible to save on connections byemploying the technique of multiplexing when the electrooptic effectused is non-linear, which is the case for standard liquid-crystaltechnologies. The pixels are grouped together by a matrix system into ngroups each of m pixels. These are, for example, n rows and m columns inthe case of matrix screens, or n numerals and m parts of numerals fornumerical displays. In the sequential addressing mode, which is usedmost often, a single row is selected at a time and then selection passesto the next row and so on until the last row. During the row selecttime, the column signals are applied at the same instant to all thepixels of the row. This method allows an image to be addressed in atotal time equal to the row address time multiplied by the number ofrows n. With this method, m+n connections are sufficient to address ascreen of m×n pixels, where m is the number of columns of the matrix inquestion. A multiplexed matrix screen is illustrated in FIG. 5.

The electrical signal seen by the pixel is the difference between thesignal applied to the row and the signal applied to the column, withwhich the pixel intersects.

This screen principle illustrated in FIG. 5 is called a “passivescreen”. A row electrode is common to all the pixels of this row and acolumn electrode is common to all the pixels of this column.

The conducting electrodes must be transparent. The material used by allmanufacturers is ITO (a mixed indium tin oxide).

The drawback of multiplexing a passive screen is that a pixel issensitive to the column signals throughout the image address time, andnot only during the period of activation of its row. That is to say apixel of the screen receives, during the image write time, in successionthe column signals of its entire column. The signals applied to thepixel outside the time for selecting its row may be considered asparasitic signals, which come into play in the electrooptic response ofthe liquid-crystal pixel. More precisely, for TN or STN-type passivematrices or one of their variants under standard operating conditionsthe state of the liquid crystal in a pixel depends almost exclusivelyonly on the RMS (root mean square) value of the voltage that is appliedto it during the image address time. Therefore the final state of theliquid-crystal molecules, i.e. in fine the optical transmission of thepixel, is determined by the RMS value of the voltage applied during theimage address time. In addition, the image refresh rate is imposed bythe eye's sensitivity to flicker, typically 50 Hz. Sensitivity to theRMS value and a set rate have the consequence of limiting the number ofrows of the screen, expressed by the Alt and Plesko criterion (document[2]). The multiplexing of a passive screen is therefore suitable formedium-resolution LCDs.

Multiplexing Applied to a BiNem

To be multiplexed, the pixel signal must be decomposed into a rowsignal, common to all the pixels, and a column signal which, dependingon its sign, will allow either the U texture or the T texture to beobtained. FIG. 6 shows an example of row and column signals forproducing the suitable pixel signal.

The row signal (FIG. 6 a) has two levels: the first level provides avoltage A1 for a time τ₁ and the second level provides a voltage A2 fora time τ₂. The column signal (FIG. 6 b for switching to the U state andFIG. 6 c for switching to the T state) of amplitude C is applied onlyfor the time τ₂, this being positive or negative depending on whetherthe image is to be erased (i.e. to obtain the U state) or to be written(i.e. to obtain the T state). A time τ₃ separates two row pulses. FIGS.6 d and 6 e illustrate the signals applied to the terminals of an erasedpixel (switching to U) and to the terminals of a written pixel(switching to T), respectively.

The conditions to be fulfilled for these signals are:

-   -   A1=P1; A2−C=P2U; A2+C=P2T.

In the above numerical example, one solution is:

-   -   A1=20 V, A2=10.5 V, C=2.5 V; hence P2U=8V and P2T=13 V; τ₁=τ₂=1        ms.

These signals are very simple and allow all their parameters to beeasily adjusted to the characteristics of the screen.

The switching principle based on the waveform of the falling edge of thepixel signal is specific to a BiNem.

To take account of problems of degradation of certain liquid-crystalmaterials by electrolysis when they are subjected to a DC voltage, it isoften useful to apply signals of zero or almost zero mean value to thepixels. Techniques for converting the basic signals of FIG. 6 intosymmetrical signals of zero mean value are described in document [4].

Limitations of Multiplexing for a BiNem

Rate Limitation

In multiplexed addressing one row at a time, the time to write an imageof n rows is equal to n times the address time for one row.

In the above example, the row time is 2 ms, i.e. in the case of 160rows, an image time of 320 ms and in the case of 480 rows an image timeof 960 ms.

These image write times are short and are incompatible with thedisplaying of moving images.

One solution for improving the image write rate, by addressing severalrows at a time, is described in document [3].

However, this technique is limited to increasing the speed by a factorof the order of 2 or 3, insufficient for reaching the rate of around 50Hz in a medium-resolution display (typically having 300 rows).

This limitation is common to BiNems and to standard liquid crystals.

Sensitivity to Parasitic Signals

In multiplexed mode, a pixel (N, M) is subjected to the pixel addressrow signal and to the column signal that relate to it. However, it isalso subjected to the column signals of amplitude +/−C that are intendedfor the other pixels of column M of which it forms part, with a periodT=τ₁+τ₂+τ₃ (FIG. 7). These signals are parasitic signals that affect thepixel voltage during the image write time. This is because a nematicliquid crystal is sensitive to the root mean square voltage to which itis subjected. The optical appearance of the display is thereforedisturbed during image writing.

One solution for reducing this effect has been proposed in document [4].The duration of the column signal is reduced relative to the duration ofthe second level of the row signal, making it possible to reduce theparasitic signals and therefore the optical perturbation of the imageduring writing. However, this reduction is limited by several factors:when the operating temperature is lowered, it is necessary to increasethe amplitude of the column signals in order to continue to switchbetween U and T. In addition, to make all the pixels of a cell switch,it is necessary to choose an amplitude C that is higher than thatnecessary for a single pixel, since the technology introduces spatialdispersion in the switching voltages, which must be taken into account.

Standard liquid crystals are also sensitive to the RMS value of theapplied voltage, but this value influences the state of the pixel notonly during writing of the image but permanently, since they must beaddressed constantly in order to exhibit the desired optical state.

Sensitivity to the Electrical and Geometrical Characteristics of theAddressing Track

According to what was described above, one specific characteristic of aBiNem is that switching to the T texture means that a steep voltage fallmust be applied to the pixel. A signal of the double-level type having asufficient voltage drop propagates along the entire ITO row as far asthe last pixel of the row. Because of the electrical characteristics(Rs) of the row, the waveform of the pulse will be modified during itspropagation. It is of fundamental importance for its waveform onarriving at the final pixel to be always compatible with switching to T.We will now examine in a typical example the variation in the fallingslope of the signal applied to a row during propagation along this row.

To simplify matters, we will assume a square-wave signal of 20 Vamplitude for switching to T. For this voltage, it has been determinedthat switching to T is effected if the voltage drop (from 90% to 10% ofits value) is effected in less than a time Tt of approximately 30 μs.

Let us consider a display of M columns and N rows, of length L and width1 (see FIG. 8). The length of a pixel is L/M=p. The width of a pixel is1/N=a. The region of separation between the rows and columns isneglected and the active area of the pixel is p×a.

The equivalent circuit diagram for a row is given in FIG. 9. Each pixelis equivalent to a tripole comprising a series resistor Rpx and aparallel capacitor Cpx that are defined as follows:

-   -   Rpx=p/a.R_(s), where R_(s) is the surface resistance of ITO. The        resistivity of the liquid crystal is neglected.        Cpx=C _(LC)=ε₀ε_(r) ap/e,        where    -   e is the thickness of the liquid-crystal cell    -   ε₀ is the dielectric constant of free space and    -   ε_(r) is the relative dielectric constant of the liquid crystal.

The time constant Rpx.Cpx associated with each pixel is therefore:Rpx.Cpx=R _(s)(ε₀ε_(r) /e)p ².

Propagation along the line is given by a diffusion equation. Theimpedance of the line is calculated analytically. The characteristictime Td at the end of the row of length L is Td=R_(s)(ε₀ε_(r)/e)L².

The rise or fall (90%-10%) time at the end of a row for a step appliedat the start of a row is 0.9 Td.

FIG. 10 a shows the calculated waveform of the fall of the electricalsignal applied to pixel M (pixel at the end of the row) for row lengthsof 30, 60, 90, 120 and 150 mm with the following typical numericalvalues:

-   -   ε₀=8.854×10⁻¹² F/m; ε_(r)=15; e=1.5 μm;    -   a=p=200 μm; R_(s)=30Ω; R_(contact)=1 kΩ.

In FIG. 10 a, it may be seen that beyond a length of 120 mm, the fall(90%-10%) takes place in a time Tt of more than 30 μs. Switching to theT state is therefore no longer possible.

One solution is to reduce the surface resistance R_(s) of ITO. FIG. 10 bemploys the same parameters as in FIG. 10 a, but with R_(s)(ITO)=15Ω. Bycomparing the two series of curves, it may be seen that the 30 μsthreshold is reached for a length of approximately 150 mm, compared witha length of 120 mm in the case of R_(s)=30Ω. Reducing R_(s) by a factorof 2 makes it possible to increase the length of the row only by thesquare root of 2.

However, reducing R_(s) means increasing the thickness of the ITO andtherefore the cost of the ITO. 15Ω would be a reasonable value, while 5Ωwould be a limit value.

The relationship 0.9R_(s)(ε₀ε_(r)/e)L²<30 μs therefore limits the lengthof the row of the screen that may be addressed. This limitation isspecific to the mode of switching a BiNem, which is sensitive to thewaveform of the applied electrical signal. Standard liquid crystals (forexample TN and STN) are sensitive to the root mean square of the appliedelectrical signal, which is less affected by this attenuation.

Active Addressing of Standard Liquid Crystals

Principle of Active Addressing

The principle of actively addressing a liquid-crystal pixel, for exampleusing a TFT (thin film transistor), generally of the MOS type, isillustrated in FIG. 11. Each pixel is addressed via a TFT switch 40 thatconnects it to its column 45 during the addressing phase (row time) andisolates it from the external environment during the sustain phase(frame time or time to address the entire image), thereby making itpossible to maintain a constant voltage at its terminals throughout theframe time. The switch is activated by sequentially scanning the rows 46of the screen (as in the case of multiplexed addressing), or a closingvoltage (to turn the transistor on) is applied for the corresponding rowtime and an opening voltage (to turn the transistor off) is appliedwhile addressing the other rows. The row 46 is thus connected to thegate 41 of the MOS transistor 40 that controls the turning-off orturning-on of the transistor, the column 45 is connected to the source42 and the drain 43 is connected to the drive electrode 47 of theliquid-crystal pixel. On the other face of the pixel, the back electrode48 is common to all the pixels.

The equivalent circuit diagrams for a pixel when the transistor is onand off are given in FIGS. 12 a and 12 b, respectively.

Each actual pixel of a liquid crystal may be likened to a cellcomprising a capacitor C_(LC) in parallel with a resistor R_(LC).

In the on state, as illustrated in FIG. 12 a, a current flows throughthe resistor R_(on) of the transistor and charges the aforementionedcell (C_(LC), R_(LC)).

In the off state, as illustrated in FIG. 12 b, a leakage current maydischarge the capacitor C_(LC) through the parallel resistor R_(LC).

To minimize leakage during the sustain phase and parasitic inter-pixelcoupling, a storage capacitor C_(S) is generally added in parallel withthe capacitor C_(LC) of the liquid crystal, at the expense ofcomplexifying the TFT technology.

The important electrical parameters in a TFT-addressed liquid-crystalscreen are:

-   -   R_(on) and R_(off) of the transistor;    -   Cpx=C_(LC)+C_(s): total capacitance of the pixel; and    -   R_(LC): resistance of the LC.

In addition, the tracks that form the rows 46 and the columns 45 thatcarry the electrical signal to the pixel have non-zero resistivities.The tracks 45 and 46 that intersect form, at the point of intersection,parasitic capacitors. The resistance and capacitance that aredistributed along the track result in a distortion and a phase shift ofthe signal (idem ITO). The following terms are defined:

-   -   R_(ct): total resistance of the column track that transports the        data to the pixel;    -   C_(ct): total capacitance of the column track that transports        the data to the pixel.

The liquid-crystal alignment layers (not illustrated in FIG. 11) aredeposited on the electrodes 47, 48, as in the case of multiplexedpassive LCDs.

Advantages of Active Addressing

Rate

Typically, 75 Hz corresponds to a frame time of 13 ms, and 13 μs per roware needed to address 1000 rows. When the transistor is on, the row timeto charge the capacitor of the liquid crystal must be of the order ofone to a few tens of μs. This imposes a low value on the R_(on) of thetransistor. If this condition is met, high address rates forhigh-resolution images are possible with this method.

Resolution

When the transistor is off, the voltage is maintained at the terminalsof the pixel, which is isolated from the parasitic column signalsthroughout the entire frame time. The multiplexing constraint (Alt andPleshko criterion) is lifted and a large number of pixels may beaddressed. The limitation is, in order to maintain a given grey level,that the voltage at the terminals of the pixel is maintained at a givenvalue and does not vary more than the voltage difference between twogrey levels. To do this, the leakage resistance of the pixel must beless than a certain value, which imposes a constraint both on theR_(off) of the transistor and on the resistance R_(LC) of the liquidcrystal.

A few figures for a TFT addressing 1000 rows at 75 Hz, with 256 greylevels, are the following:

-   -   frame time: 13 ms;    -   row (gate open) time T_(g): 13 μs;    -   application of the voltage to the terminals for the pixel: this        voltage must change by approximately 3 V in Tg=13 μs.

Maintaining the initial grey level: the voltage at the terminals of thepixel must be maintained with a variation of less than 10 mV during theframe time (13 ms). This constraint imposes a high R_(off) of thetransistor and a high resistance of the liquid crystal.

The so-called “standard” TFTs use a thin amorphous silicon (a-Si) layerand are coupled to the TN (twisted nematic) mode. For large screens ofhigh added value, the TFT is associated more with the IPS (in-planeswitching) or MVA (multidomain vertically aligned) modes that possess abetter viewing angle.

Limitation of Active Addressing: Switching of Standard LC Screens

A major limitation of TFT screens for mobile applications is their notinconsiderable power consumption. For example, a TFT matrix monitor 15inches in diagonal currently consumes close to 20 W, approximately halfof which is used for the backlighting. This situation stems both fromthe non-bistable character of standard TFT screens (that exploit the TNeffect), but also from the low luminous efficiency of TFT technology.One of the main causes of this low efficiency is the existence of a pooropen aperture ratio. Under these conditions, the backlighting isvirtually necessary for standard light backgrounds. The self-sufficiencyof such a TFT screen device when it is not connected to a power supplynetwork can only be short. This tendency is accentuated with TFT-IPStechnology. The viewing angle in this technology is in fact comparableto that of BiNem screens, but the existence of an array of electrodeswith a short pitch in order to apply the lateral field to the pixelsfurther reduces the open aperture ratio. The power of the lightingsystem, and therefore the consumption of the device, must be greaterthan that of a conventional TFT for equivalent brightness of the image.In addition, IPS devices require significantly higher operating voltagesthan those of conventional TFT screens. The energy budget is thereforehere too degraded. In addition, the cost burden caused by choosing theIPS technology represents a real obstacle for many high-volumeapplications. Not only is the power consumption of TFT screens high, butits non-bistable character means that it is impossible, even infavourable cases, to lower it.

DESCRIPTION OF THE INVENTION

The objective of the invention is to propose novel means for improvingthe prior art.

This objective is achieved within the context of the present inventionby means of a display device comprising a bistable nematicliquid-crystal matrix screen with anchoring breaking, characterized inthat it comprises:

-   -   components capable of switching between an off state and an on        state, these components being placed respectively between a        drive electrode associated with each pixel and a display state        control link; and    -   means capable of applying, to the input of each aforementioned        component, via the state control link, input signals comprising        at least two phases separated by a controlled time interval,        namely a first phase during which the input signal has an        amplitude sufficient to permit breaking of the anchoring of the        liquid crystal on the associated pixel, then a second phase        during which the amplitude of the input signal is controlled in        order to select one of the two bistable states of the liquid        crystal, the time interval between the two phases being adapted        in order to break the anchoring of the liquid crystal on the        said associated pixel before the second input signal phase is        applied.

Also more precisely, within the context of the present invention, theaforementioned components are preferably formed from switches drivenbetween an off state and an on state by an address signal, and areplaced respectively between a drive electrode associated with each pixeland a display state control link, and the device furthermore includesmeans capable of defining address signals that comprise at least twoactive phases controlling a switch in the on state, the said phasesbeing separated by a controlled time interval, and capable of applying,to the input of each driven switch, via the state control link, insynchronism with the active phases of the address signal selectivelyturning the latter on, input signals comprising at least two phases,namely a first phase during which the input signal has an amplitudesufficient to permit breaking of the anchoring of the liquid crystal onthe associated pixel, then a second phase during which the amplitude ofthe input signal is controlled in order to select one of the twobistable states of the liquid crystal, the time interval between the twophases being adapted in order to break the anchoring of the liquidcrystal on the said associated pixel before the second input signalphase is applied.

We will call this structure “active BiNem”.

For the purposes of the present invention, the expression “matrixscreen” must not be considered as being limited to a regular arrangementof pixels in rows and columns. It encompasses any arrangement of pixelsin the form of n groups of m associated elements, for example n numeralseach formed from m elements.

The present invention also relates to a method for electricallycontrolling a bistable nematic liquid-crystal matrix screen withanchoring breaking, characterized in that it comprises:

-   -   the provision of components capable of switching between an off        state and an on state, these components being placed        respectively between a drive electrode associated with each        pixel and a display state control link;        and in that it comprises the steps consisting, for the        electrical control, in:    -   applying, to the input of each aforementioned component, via the        state control link, input signals comprising at least two phases        separated by a controlled time interval, namely a first phase        during which the input signal has an amplitude sufficient to        permit breaking of the anchoring of the liquid crystal on the        associated pixel, then a second phase during which the amplitude        of the input signal is controlled in order to select one of the        two bistable states of the liquid crystal, the time interval        between the two phases being adapted in order to break the        anchoring of the liquid crystal on the said associated pixel        before the second input signal phase is applied.

According to another advantageous feature of the present invention, thescreen according to the present invention uses two textures—one auniform or slightly twisted texture in which the molecules are at leastapproximately parallel to one another and the other that differs fromthe first by a twist of about +180° or −180°.

Although the use of active addressing, via respective controlledswitches, offers many advantages within the context of a BiNem-typescreen, that is to say using a bistable nematic liquid crystal withanchoring breaking, a person skilled in the art would have been unableto find any encouragement in the literature of the prior art to achievesuch a result.

Quite to the contrary, the required waveforms and durations of thecontrol signals for active addressing had hitherto been incompatiblewith an operational bistable screen of the BiNem type.

Moreover, the power consumption of an actively addressed liquid-crystalscreen appeared to be completely unacceptable to those skilled in theart in the context of a BiNem screen.

Finally, the cost of actively addressed screens, especially because ofthe presence of a switch associated with each pixel could not hithertohave encouraged a person skilled in the art to obtain such a result.

Dissociating the address signals and the control signals, in two phasesseparated by a controlled time interval, as proposed within the contextof the present invention, thus constitutes a considerable innovation,making it possible to achieve a real improvement over the prior art, aswill be explained in detail below.

Other features, objects and advantages of the present invention willbecome apparent on reading the detailed description that follows, inconjunction with the appended drawings, given by way of non-limitingexamples, in which:

FIG. 1, described above, shows schematically a BiNem screen according tothe prior art;

FIG. 2, described above, shows an example of a square-wave pixel signalfor switching to the T state, for such a BiNem screen;

FIG. 3, described above, shows an example of a pixel signal with agradual falling edge for switching to the U state, for such a BiNemscreen;

FIG. 4, described above, shows an example of a two-level pixel signal,allowing selection of the texture according to the P2 value of thesecond level of the pulse applied to the terminals of the pixel, forsuch a BiNem screen;

FIG. 5, described above, shows schematically a multiplexed matrixscreen;

FIG. 6, described above, shows an example of row and column signals fora pixel of a BiNem screen in multiplexed mode;

FIG. 7, described above, shows an electrical signal at the terminals ofa pixel of a BiNem screen in multiplexed mode;

FIG. 8, described above, gives another representation of a multiplexeddisplay;

FIG. 9, described above, illustrates an equivalent circuit diagram for arow of a multiplexed liquid-crystal display, of the BiNem screen type inmultiplexed mode;

FIG. 10, described above, shows the variation in the waveform of thefalling edge of the voltage applied to a pixel of a BiNem-type screen inmultiplexed mode, during propagation along a row, for an ITO surfaceresistance of 30Ω in FIG. 10 a and 15Ω in FIG. 10 b, respectively;

FIG. 11, described above, shows schematically the general principle ofactive addressing, in accordance with the prior art;

FIG. 12, described above, shows the equivalent circuit diagram of aliquid-crystal pixel addressed by a transistor, in the on state in FIG.12 a and in the off state in FIG. 12 b, respectively;

FIG. 13 shows the addressing of an “active BiNem” screen according tothe present invention, for switching as required to the U state or tothe T state, according to a first implementation option comprising threesuccessive phases or stages of applying control signals: more precisely,FIG. 13 a shows the address signal applied to the gate of a transistor;FIG. 13 b shows two variants of the state control signal applied to thesource of the transistor, in order to obtain the U and T statesrespectively; FIGS. 13 c and 13 d show the resulting signal available onthe drain of the transistor and consequently on the pixel, in the caseof switching to the U state and in the case of switching to the T staterespectively; and FIG. 13 e shows schematically a second address signaloffset with respect to that of FIG. 13 a and intended for a second rowof the display;

FIG. 14 shows the equivalent circuit diagram of a BiNem-typeliquid-crystal pixel addressed by a transistor, for example of the TFTtype, according to a second implementation option comprising twosuccessive phases or stages of applying control signals;

FIG. 15 shows schematically the addressing of an “active BiNem” screenaccording to the present invention for switching, as required, to the Ustate or to the T state according to a second implementation optioncomprising two successive phases or stages of applying control signals:more precisely, FIG. 15 a shows the address signal applied to the gateof a transistor; FIG. 15 b shows the state control signal applied to thesource of the transistor; FIGS. 15 c and 15 d show the resulting signalavailable on the drain of the transistor and consequently on the pixel,in the case of switching to the T state and in the case of switching tothe U state respectively; and FIG. 15 e shows schematically a secondaddress signal offset with respect to that of FIG. 15 a and intended fora second row of the display;

FIG. 16 shows schematically the electrical voltage at the terminals of apixel according to the present invention for switching to the T state;

FIG. 17 shows schematically the row address voltage applied to the gateof a transistor in the case of the first option according to the presentinvention;

FIG. 18 shows an example of a row address voltage applied to the gate ofa transistor in the case of the second option according to the presentinvention;

FIG. 19 shows schematically an example of addressing an active BiNemaccording to the first option, comprising three successive controlvoltage applications, for a simulated pixel signal for switching to a Ttexture, FIG. 19 b showing a partial enlarged view of the rising andfalling edges of the signal of FIG. 19 a;

FIG. 20 shows an illustration similar to FIG. 19 for a simulated pixelsignal for switching to the U texture;

FIG. 21 shows the addressing of an active BiNem according to the secondoption according to the present invention, comprising two successivecontrol voltage applications for a simulated pixel signal for switchingto the T texture, here again FIG. 21 b showing a partial view on anenlarged scale of the rising and falling edges of the signal of FIG. 21a;

FIG. 22 shows a view similar to FIG. 21 a for a simulated pixel signalfor switching to the U texture;

FIG. 23 shows schematically an embodiment according to the presentinvention comprising switching means in the form of a diode for eachpixel;

FIG. 24 shows schematically another embodiment according to the presentinvention, comprising switching means in the form of two back-to-backdiodes for each pixel;

FIG. 25 shows the response of a diode used in the embodiment of FIG. 23;and

FIG. 26 shows the response of two diodes mounted back to back used inthe case of the embodiment of FIG. 24.

The overall structure of the screen according to the present inventionis identical to the structure of a conventional TFT screen asillustrated in FIG. 11.

The essential differences from such a conventional TFT screen are thefollowing:

-   -   one of the standard orientation layers is replaced with a weak        zenithal anchoring orientation layer 34 specific to the BiNem;    -   the cell is made with a smaller thickness than in the case of        standard technology; and    -   the cell is filled with a BiNem-tailored liquid crystal so as to        obtain the two textures U and T as illustrated in FIG. 1, and        also operation of the cell in BiNem mode.

Thus, typically, in the case of the present invention, for each pixeldefined between two electrodes 22, 32 facing each other and placed onone of the two plates or substrates 20, 30 respectively, one of theelectrodes is connected to the drain 41 of a respective transistor 40,forming a switch, the source 42 of the latter is connected to a statecontrol track or link, for example a column 45, in order to receive astate control signal, the gate 41 of the transistor is connected to adrive or address track or link, for example a row 46, in order toreceive a drive or address signal, and the back electrode is connectedto a common potential, for example earth, this being common to all thepixels.

For a screen of n×m pixels grouped together in the form of n groups of melements, for example m rows of m columns, n×m controlled switches 40are thus provided, an array of n conducting tracks forming address rowsfor the latter and an array of m conducting tracks forming columns forcontrolling the transistors.

When no signal is applied to the gate 41 of a transistor 40, it is off,that is to say non-conducting.

On the other hand, when a suitable signal is applied to the gate 41 ofthis transistor 40, it is turned on. The voltage applied to the source42 of the latter then appears on the drain 43 of the transistor andconsequently on the associated electrode 47 of the latter.

The pixel formed by the liquid crystal placed between two electrodesconstitutes a capacitor capable of maintaining this voltage at itsterminals when the transistor is switched to the off state, that is tosay when the address signal applied to its gate is cut off.

The subsequent variation in this voltage, before application of a newaddress signal and a new control signal, depends on the impedancedefined between the two electrodes of the pixel.

Hereafter, the aforementioned switch transistors associated with eachpixel respectively will be called TFTs (thin film transistors).

However, the present invention must not be considered as being limitedto any one technology for producing the controlled switches. Itencompasses any technology capable of carrying out such a function. Forexample, a system based on one or more diodes may be envisaged.

The TFTs 40 make it possible to isolate all the pixels of the screenexcept those associated with the addressed row 46, which are eachconnected via their column track 45 to a column driver.

Conventional standard addressing of TFTs requires all the pixels in eachframe to be addressed and controlled, whereas the bistability of theBiNem allows only the pixels whose state is modified between each frameto be selectively controlled. Because of the bistability, it is thuspossible to achieve highly individual addressing. We will call this mode“selective addressing”.

More precisely, in the context of the present invention, at eachaddressing of a row, the pixels that have to change state must receive aswitching signal on the source of their associated transistor, in orderto provide, in succession, anchoring breaking followed by selection, theother pixels possibly remaining earthed, that is to say receiving a zerovoltage via their transistor placed in the on state (this is becausesuch a zero voltage cannot break the anchoring and consequently cannotmodify the state of the pixel). The power consumption may thus begreatly reduced, almost zero in the case of slowly varying images. Thecontrast and brightness of the screen will be optimum in this case, theswitching of a pixel via the intermediate switching states not appearingat each frame but only when this pixel has to change state. Theflickering of the image is thus completely eliminated.

The addressing of the active BiNem takes place according to theinvention several times, in the form of at least two phases separated bya controlled time interval. The present invention is thus fundamentallydifferent from the addressing of a standard TFT, which takes place oncesince standard liquid crystals become oriented simply according to thevalue of the applied field.

The essential function of the address and control signals according tothe present invention is to produce a correct signal, for example withtwo levels, at the terminals of the pixel by firstly applying, during afirst phase, a control voltage P1 (for a row address time Tg) via thesource of the transistor, in order to achieve breaking, then byapplying, after a time Tc called the breaking time, during a secondphase, a control voltage P2U or P2T (for a row address time Tg′ that maybe different from Tg) again via the source of the transistor, making itpossible to obtain the U texture or the T texture. It may also benecessary to apply a third voltage, close to or equal to zero, during asubsequent third phase.

We will firstly describe the two addressing options (with three phasesand two phase respectively) for switching between U and T, and we willthen enlarge the addressing concept to the construction of a BiNem withgrey levels.

Switching Between U and T

Option 1: 3-Phase Addressing

This option is illustrated in the timing diagram of FIG. 13.

In FIG. 13, the frame time is denoted by TRA, that is to say the addresssignals illustrated in FIG. 13 a and the state control signalsillustrated in FIG. 13 b are repeated with a repetition period TRA (thenon-selective addressing case or the selective addressing case when thepixel changes state) or a multiple of TRA (selective addressing casewhen the pixel does not change state at each frame).

As illustrated in FIG. 13 a, the address voltage is applied three timesin succession to the gate 41 of a transistor 40 in order to switch it tothe on state:

-   -   in the first phase, the address signal has a duration Tg;    -   in the second phase, the address signal, whose rising edge is        delayed by Tc relative to the first, has a duration Tg′; and    -   in the third phase, the address signal whose rising edge is        delayed by Ts relative to the second has a duration Tg″.

The times Tg, Tg′ and Tg″ may be the same or different.

The time Tc is defined so as to be sufficient to ensure that the weakanchoring 34 on the substrate 30 is broken before the select signal ofduration Tg′ is applied.

As illustrated in FIG. 13 b, three control voltages are applied insuccession to the pixel via the associated transistor 40, in synchronismwith the aforementioned address voltages of duration Tg, Tg′ and Tg″(the rising edges of these three voltages are also separated by a timeTc and then Ts):

-   -   first phase (duration Tg) a control voltage P1 is applied to the        source of the transistor in order to achieve breaking; and    -   second phase (duration Tg′, after a time Tc): a control voltage        P2T or P2U is applied to the source of the transistor depending        on the texture to be obtained.

In order to switch to the T state, the two (high and low) regions shownschematically in FIG. 4 may be used for P2T.

If it is the low value of P2T that is chosen, this may be chosen to bezero or very low, as there is in this case no constraint associated withmultiplexing requiring selection between T and U to be made with thesign of a single column signal C. Since the voltage jump is larger (P1compared with P1-P2T), the switch to T is facilitated. Such a signal isof the square-wave type illustrated in FIG. 2.

For switching to the U texture, the voltages P2U of FIG. 4 are suitable;

-   -   third phase (duration Tg″, after a time Ts): reset to zero with        a zero or very low voltage POT or P0U.

As indicated above, during the second phase Tg′, for the T texture, thetwo (high and low) regions illustrated in FIG. 4 may be used for P2T. Inthe low P2T case, switching to T is initiated during the secondaddressing Tg′. In the high P2T case, switching to T is initiated duringthe third addressing Tg″, at the moment of the voltage drop between P2Tand P0T.

For the U texture, resetting to zero after application of P2U allows theliquid-crystal molecules to reach a rest state before a new addressingsequence. Therefore, after a time Ts called the select time, a zero oralmost zero voltage P0U is applied for a time Tg″ (new opening of therow) to the terminals of the pixel. P0U is not necessarily equal to P0T.

The resulting control signal obtained on the drain of the transistor,and consequently on the pixel, for a low P2T voltage during the phaseTg′ is illustrated in FIG. 13 c. During Tg, the capacitor of the pixelis charged to the voltage P1. After Tg, this capacitor possiblydischarges through the parallel leakage resistors. The voltage at theterminals of the pixel is reset to P2T during Tg′. The capacitorpossibly discharges after Tg′. Finally, the voltage at the terminals ofthe pixel is reset to zero during Tg″. This signal results in the Tstate.

Likewise, the resulting control signal obtained on the drain of thetransistor, and consequently on the pixel, for a voltage P2U during thephase Tg′ is illustrated in FIG. 13 d. During Tg, the capacitor of thepixel is charged to the voltage P1. After Tg, this capacitor possiblydischarges through the parallel leakage resistors. The voltage at theterminals of the pixel is reset to P2U during Tg′. The capacitorpossibly discharges after Tg′. Finally, the voltage at the terminals ofthe pixel is reset to zero during Tg″. This signal results in the Ustate.

In general, the principle described above according to the presentinvention may be extended to x successive applications each of durationTg^(x), separated by control time intervals Tc followed by variousTs^(x), of various control signals. The advantage of increasing thenumber of control signal application phases is to better approximateoptimum signal for switching to the U state, this being a continuouslydecreasing ramp. Addressing with four transitions makes it possible toapproximate the ramp with three levels, etc. The drawback is an overallrow time that increases with the number of transitions. For the samestate control, each row is therefore addressed x times with a frameperiod TRA (non-selective addressing case or selective addressing casewhen the pixel changes state) or a multiple of TRA (selective addressingcase when the pixel does not change state at each frame).

Between the addressing phases Tg^(x) for one row, other rows may beaddressed.

Thus, FIG. 13 e schematically illustrates an example of an addresssignal offset relative to the address signal described above and capableof controlling a second row adjacent to that mentioned above.

Option 2: Two-Phase Addressing

This option is illustrated in the timing diagram of FIG. 15.

Here again, in FIG. 15 the frame time is denoted by TRA, that is to saythe address signals illustrated in FIG. 15 a and the state controlsignals illustrated in FIG. 15 b are repeated with an addition periodTRA (non-selective addressing case or selective case when the pixelchanges state) or a multiple of TRA (selective addressing case when thepixel does not change state at each frame).

As illustrated in FIG. 15 a, the address voltage is applied twice insuccession to the gate 41 of a transistor 40 in order to switch thelatter to the on state:

-   -   in the first phase, the address signal has a duration Tg;    -   in the second phase, the address signal, the rising edge of        which is delayed by Tc relative to the first, has a duration        Tg′.

The times Tg and Tg′ may be identical or different.

The time Tc is defined to be sufficient to ensure that the weakanchoring 34 on the substrate 30 is broken before the select signal Tg′is applied.

As illustrated in FIG. 15 b, two control voltages are applied insuccession to the pixel via the drain 43 of the associated transistor40, in synchronism with the aforementioned address voltages Tg and Tg′(separated by a time Tc called the breaking time);

-   -   first phase (duration Tg): a control voltage P1 is applied to        the source of the transistor in order to achieve breaking; and    -   second phase (duration Tg′, after a time Tc): a control voltage        P2T or P2U is applied to the source of the transistor depending        on the texture to be obtained.

Let P1 f be the voltage of the terminals of the pixel at the start ofthe second transition Tg′ (cf. FIG. 16).

For the T texture, P2T must be low enough (ideally P2T≈0) for thevoltage jump between P1 f and P2T to allow switching to the T state.Likewise, the voltage P1 f must remain high enough for the voltage jumpbetween P1 f and P2T to allow switching to the T state.

In the case of zero P2T, since the voltage jump is greater (P1 fcompared with P1 f-P2T), the switching to T is facilitated (the signalapplied to the pixel is then of the square-wave type illustrated in FIG.2). A second advantage of a zero P2T is that the liquid-crystalmolecules are at rest during the next switching.

The high P2T value (cf. FIG. 4) cannot be used here since there would beno resetting to zero of the voltage P2T, which would remain appliedthroughout the frame time TRA.

For switching to the U state, the voltage P2U may be close to thevoltage P1 f so as to obtain a fall in the form of a continuous ramp. Adecreasing ramp signal waveform as described in FIG. 3 is thus obtainedby means of the discharge current obtained in the leakage resistorspresent at the terminals of the pixel. This signal waveform is wellsuited to switching to the U state.

To obtain the optimum discharge time, that is to say the time sufficientto switch to the U state, but less than the frame time TRA, it may benecessary to add a discharge resistor RF to the terminals of the pixel,as illustrated in FIG. 14.

Switching to the T State:

FIG. 15 c illustrates the resulting control signal obtained on thepixel, for a low P2T voltage during the phase of duration Tg′. DuringTg, the capacitor of the pixel is charged to the voltage P1 i. After Tg,the capacitor of the pixel possibly discharges through the parallelleakage resistors. The voltage is thus equal to P1 f before the secondaddressing transition of duration Tg′, where P1 f<P1 i. The voltage atthe terminals of the pixel is reset to P2T during Tg′. P1 f must be suchthat P1 f-P2T allows switching to the T state. The capacitor dischargesafter Tg′ in order to obtain a zero voltage before the end of the frameTRA. This signal results in the T state.

Switching to the U State:

Likewise, FIG. 15 illustrates the resulting control signal obtained onthe drain of the transistor, and consequently on the pixel, for avoltage P2U during the phase Tg′. During. Tg, the capacitor of the pixelis charged to the voltage P1 i. After Tg, this capacitor dischargesthrough the parallel leakage resistors. The voltage is thus equal to P1f before the second addressing transition of duration Tg′, where P1 f<P1i. The voltage at the terminals of the capacitor of the pixel is resetto P2U during Tg′. The capacitor discharges after Tg′ in order to obtaina zero voltage before the end of the frame TRA. This signal results inthe U state.

Because of the existence of a discharge resistor R_(F), the value P1f-P1 i is greater in the case of option 2 than option 1.

For the same state control, each row is therefore addressed twice (Tgand Tg′) with a frame period TRA. Between these addressing phases,separated by a time Tc, other rows may be addressed.

Here again, FIG. 15 e thus illustrates schematically an example of anaddress signal offset relative to the address signal described above andcapable of controlling a second row adjacent to that mentioned above.

Conditions for Obtaining Switching with the Active BiNem

FIG. 16 shows in detail the variation of the voltage at the terminals ofa pixel, for switching to the T state, which is the most criticalswitching (since it requires an abrupt drop at a time Tt of less than athreshold of around 30 μs).

Four successive stages may be distinguished in this variation.

1. EC Phase of Duration Tg: Establishment of the Anchoring-BreakingVoltage at the Terminals of the Pixel.

The voltage P1 i that must be reached at the end of the time Tg, i.e. atthe end of the conducting period of the transistor, must be greater thanthe anchoring-breaking voltage V_(c), typically 15 to 18 V at roomtemperature:

-   -   P1 i>V_(c)≈15 to 18 V;    -   Tg around 20 μs.

The voltage to be reached does not have to be of precise value, it needonly exceed V_(c) in order to be able to break the anchoring. Inaddition, the P1 anchoring-breaking voltage may be different forswitching to the U state or for switching to the T state. In contrast,in the case of a standard TFT with a TN or other liquid crystal, a veryprecise value must be obtained in the time Tg in order to obtainreliable grey levels. For the EC phase, the constraint on thecombination of a TFT and an active BiNem liquid crystal according to thepresent invention is therefore less than in the case of a TFT coupled tostandard liquid crystals.

The electrical parameters involved in charging to P1 are: the resistanceR_(on) of the transistor, the capacitance of the pixel Cpx=C_(LC)+C_(s),the time to propagate along the column track and its resistance, thesebeing determined from R_(ct) and C_(ct).

2. C Phase of Duration Tc-Tg: Anchoring Breaking.

During the time Tc-Tg after Tg, the transistor is off and the voltage P1must be maintained above V_(c) in order to break the anchoring. Let P1 fbe the voltage at the terminals of the pixel at the end of the time Tc:P1 f>V_(c)≈15 to 18 V.

Typically, a reduction by a few volts is acceptable during the timeTc-Tg. The voltage P1 does not need to be maintained at a precise level,unlike in the case of a standard TFT generating grey levels. In the caseof the C phase, the constraint on the combination of a TFT and an activeBiNem liquid crystal according to the present invention is thereforeless than that for a TFT and a standard liquid crystal.

Typically, the time Tc-Tg must be greater than or equal to τ₁ (cf. FIG.4), during which time a voltage greater than V_(c) must be maintained inorder to break the anchoring, typically τ₁≈1 ms. With Tg=20 μs andTc−Tg=τ₁, 50 other rows may be addressed during the phase of breakingone row.

The electrical parameters involved during the sustaining of P1 are: thecapacitance of the pixel Cpx=C_(LC)+C_(S), the resistance R_(LC) of thelatter and, possibly, R_(F) if a leakage resistance is added asdescribed in option 2.

3. ES Phase of Duration Tg′: Establishment of the Texture Select Signal

As in the case of passive multiplexing, it is the switching to the Ttexture that is most tricky, since a rapid fall, in a time Tt, from P1f>V_(c) to P2T is needed. Typically Tt is around 30 μs, i.e. of theorder of magnitude of the gate open times. To optimize the rate, it isbeneficial to take Tg′≦Tt≈30 μs. The condition for the voltage to fallfrom P1 f to P2T in a time of the order of Tg is overall equivalent tothat of the EC phase: the constraint on the TFT is similar. Theelectrical parameters involved during the ES phase are the same as inthe case of the EC phase.

4. A Fall to Zero of the Select Signal takes Place Either Via a ThirdTransition, with Resetting to Zero (in the Case of Option 1), or by theVoltage Leakage at the Terminals of the Pixel (in the Case of Option 2).

Production of Grey Levels in an Active BiNem

It is possible to produce grey levels in active BiNem mode according tothe present invention by creating, within a pixel, microdomains of T andU textures, the size and the density of which are controlled (cf.document [6]). Control is achieved by precisely controlling the voltageP2 of the second level (during the S phase of the addressing).

It will be worthwhile referring to document [6] for the implementationof such a process.

This process will therefore not be described in detail hereafter.

However, it will be recalled here that grey levels may be controlled bycontrol means capable of producing, after anchoring breaking, mixedtextures in which the bistable textures coexist in a controlledproportion within one and the same pixel, these textures being separatedby 180° disclination lines volumewise or by 180° reorientation walls onone of the surfaces, and means for the long-term stabilization of themixed textures by transformation of volume lines into surface walls andimmobilization of these walls on the surface.

Obtaining a Zero Mean Value

The active BiNem may be switched with signals of positive or negativepolarity.

In addition, as during, passive multiplexing, problems of certainliquid-crystal materials degrading by electrolysis may arise when theyare subjected to a DC voltage. One solution for remedying thisdifficulty may consist in applying a signal of zero mean value to theliquid crystal. A signal with a zero mean value may be obtained byreversing the sign of the voltages applied to the columns from one frameto another.

Exemplary Embodiments According to the Invention

Two complete simulations of the addressing of an active BiNem screenaccording to the invention (the aforementioned options 1 and 2) werecarried out using commercial software so as to validate the criticalsteps of the addressing according to the two options. The parameterscommon to these two simulations were:

Size of the Pixel:

-   -   square pixel: W_(LC)=L_(LC)=210 μm;        Thickness of the Cell:    -   d=1.5 μm;        Characteristics of the Screen:    -   Rate: 50 Hz, i.e. a frame time of 20 ms;    -   480 rows and 640 columns (VGA resolution)-available row time: 40        μs;        Characteristics of the Liquid Crystal:    -   C_(LC)=ε₀ε_(LC)W_(LC)L_(LC)/d;    -   ε₀: permittivity of free space;    -   ε_(LC): relative permittivity of the liquid crystal.

To take account of the dielectric anisotropy of the liquid crystal, wehave considered an ε_(LC) of 5 in the case of the planar-homeotropictransition (charging of the capacitor in the EC phase) and an ε_(LC) of25 for the homeotropic-planar transition (discharging of the capacitorin the ES phase).

Resistivity of the liquid crystal: 10¹⁰ Ω.cm. This liquid crystal is ofmoderate quality as regards resistivity (LCs used in standard TFTspossess a higher resistivity, of around two orders of magnitude, i.e.10¹² Ω.cm)

Characteristics of the TFT (Corresponding to a Standard TFT Made of a-Siof the Current Prior Art):

In our model, a TFT is characterized by the following parameters:

-   -   CM=insulation capacitance per unit area: 30 nF/cm²;    -   μ₀=mobility: 0.4 cm²/V.s;    -   W=width of the TFT: 20 μm;    -   L=length of the TFT: 4 μm; and    -   C_(S)=storage capacitance=2C_(LC) (defined with    -   ε_(LC)=5, see characteristics of the liquid crystal).

These parameters allow the on mode (R_(on)) to be modelled.

Row Voltage (Applied to the Gate)

The row voltage is 30 V, with Tg=Tg′=Tg″=20 μs and Tc=Ts=1 ms.

FIG. 17 shows the row address voltage corresponding to option 1,comprising three pulses of respective duration Tg, Tg′ and Tg″.

FIG. 18 shows the row address voltage corresponding to option 2,comprising two pulses of respective duration Tg and Tg′.

Characteristics of the Metal Signal-Transporting Tracks:

-   -   R_(ct) (track): 0.1Ω; width=l_(t): 5 μm.

The voltage at the terminals of the pixel is calculated from the lastrow so as to take into account the influence of all the parasiticcoupling during propagation of the signal along the column.

Exemplary Embodiment of the Invention According to Option 1

With this option, three transitions Tg, Tg′ and Tg″ are needed, i.e. anoverall row address time of 3×20 μs=60 μs. At 50 Hz, it is thereforepossible to address 333 rows, with gate open times of 20 μs. To increasethe number of rows, it is possible to reduce the Tgs, that is to say toincrease the performance of the TFT and of the liquid crystal in orderto charge to P1 (EC phase) in a shorter time Tg and to discharge from P1(ES phase) in a shorter time Tg′.

Column Voltages:

-   -   a breaking voltage V_(col)=25 V is applied for the time Tg=20        μs, synchronized to the first address pulse coming from the row,        the objective being the charging of the pixel to the chosen        breaking voltage P1 i of 20 V in 20 μas; and    -   then, after a time Tc of 1 ms, synchronized to the second        address pulse coming from the row, the following are applied:    -   in the case of switching to the T state: a zero select voltage        for a time Tg′ of 20 μs, the objective being to pass from the        voltage P1 f to a voltage P2T, which must be less than 5 V (in        the case of P2U, between 7 and 9 V, as explained above with        regard to multiplexing the BiNem) in a time of less than Tt        (around 30 μs), in this case equal to 20 μs;    -   in the case of switching to the U state: a select voltage, of 8        V for example, for a time Tg′ of 20 μs, the objective being to        pass from the voltage P1 f to a voltage P2U, typically 8 V, in        about 20 μs; and    -   then after a time Ts, synchronized to the third address pulse        coming from the row, a zero resetting voltage is applied for Tg″        20 μs independently of the texture.        Results of the Simulations:

FIG. 19 shows the calculated signal at the terminals of the pixel forswitching to the T state. The signal generated is of the square-wavetype as illustrated in FIG. 2. This shows that the charging of the pixeltakes place correctly—a voltage slightly above 20 V is reached in 20 μs.Discharging between this same voltage (very little leakage in the caseof this “standard” TFT) and a value very close to 0 V also takes placein 20 μs. This signal is therefore completely compatible with switchingto the T texture.

FIG. 20 shows the calculated signal at the terminals of the pixel in thecase of switching to the U state.

By three addressing steps, a two-level signal of the same type as thatused for multiplexing is generated and allows switching to the U state.

The control signals for switching to the T and U states are 0 V after 2ms. The switching mechanism during the next frame is therefore notdisturbed.

A TFT with higher leakage can also be used for this option, providedthat:

-   -   P1 is maintained above V_(c) throughout the entire C phase        (typically 1 ms); and    -   no parasitic signals whose RMS value is greater than the        threshold voltage or Fredericks voltage (around 0.5 V) are sent        to the pixel.        Exemplary Embodiment of the Invention According to Option 2

With this option, two transitions Tg and Tg′ are needed, i.e. an overallrow address time of 2×20 μs=40 μs. It will be possible to address 480rows with Tg=Tg′ 20 μs.

By way of non-limiting example, a discharge resistor RF of 150 MΩ waschosen and corresponds to a discharge time of 10 ms for the maximumcapacitance of the liquid crystal.

Column Voltages:

-   -   a breaking voltage V_(col)=25 V is applied for the time Tg=20        μs, synchronized to the first address pulse coming from the row,        the objective being the charging of the pixel to the chosen        breaking voltage P1 i of 23 V in the time Tg; and    -   then, after a time Tc of 1 ms, synchronized to the second        address pulse coming from the row, the following are applied:    -   in the case of switching to the T state: a zero select voltage        for a time Tg′ chosen equal to Tg, the objective being the        discharging from the voltage P1 f to a voltage P2T, which must        be less than 5 V, in a time of less than Tt (around 30 μs), in        this case equal to 20 μs;    -   in the case of switching to the U state: a select voltage of 18        V for example, for a time Tg′=20 μs, which corresponds to a        voltage P2U such that the falling time via the discharge        resistance is less than the frame time of 20 ms.

In addition, this value allows a continuously falling signal to begenerated.

There is no resetting of the pulse to zero, and it is therefore theleakage at the terminals of the pixel that must allow resetting to 0over the duration of the frame time TRA. This resetting to zero isnecessary for the next frame, since a non-zero start voltage woulddisturb the elastic coupling and the hydrodynamic coupling, andtherefore the switching.

Results of the Simulations:

FIG. 21 shows the calculated signal at the terminals of the pixel in thecase of switching to the T state.

The signal generated is of the square-wave type as illustrated in FIG.2. This shows that the charging of the pixel takes place correctly. Avoltage of 23 V is reached in 20 μs. The discharge resistor generates avoltage drop of 3 V in 1 ms. The voltage P1 f is therefore 20 V (a fixedlimit so that P1>V_(c)≈16 V) The discharge between 20 V and a voltagevery close to 0 V also takes place in 20 μs. This signal is thereforecompletely compatible with switching to the T texture.

FIG. 22 shows the calculated signal at the terminals of the pixel in thecase of switching to the U state.

The signal generated is of the continuous slope type, as illustrated inFIG. 3. This shows that the charging of the pixel takes place correctly.A voltage of 23 V is reached in 20 μs. The discharge resistor generatesa voltage drop of 3 V in 1 ms. The voltage P1 f is therefore 20 V (afixed limit so that P1>V_(c)≈16 V) (idem switching to the T state). Thedischarge resistor therefore causes the voltage at the terminals of thepixel to decrease continuously. The decrease down to 3 V takes place in10 ms and a voltage of 0.45 V (close to the Fredericks voltage) isreached in 20 ms—a value chosen for the frame time.

The control signals for switching to the T and U states are very closeto 0 V after 2 ms and 20 ms respectively. The switching mechanism duringthe next frame is therefore undisturbed.

ADVANTAGES OF THE INVENTION Operation in Fixed Image Mode: Bistabilityand Optical Quality of the BiNem

When the screen is not being addressed and displays a fixed image, theproperties of the image are those of the BiNem. The bistability allowsthis displayed image to be sustained without any supply of energy,unlike standard liquid crystals that need to be permanently refreshed ata frequency of at least 50 Hz, resulting in increased power consumptionof the screen. The planar character of the U and T textures (nomolecules inclined to the plane of the substrate) makes it possible toachieve good optical quality (contrast, brightness) of the image at ahigh viewing angle without the addition of birefringent compensationfilms, as is the case with the TN or MVA effect.

Contribution of Selective Addressing: the Optical Quality of a FixedImage is Partly Maintained in a Moving Image

When only the pixels whose state is modified between two frames areselectively addressed, that part of the image which is not re-addressedis stable. It has a quality equivalent to that of a fixed image andgives the observer a good overall visual impression. The pixels thatswitch are only disturbed during the time needed to switch to the Tstate or to the U state, i.e. about 5 ms. The contrast and brightness ofthe screen will therefore be optimum. The transition of a pixel viaintermediate switching states does not appear at each frame, but onlywhen this pixel changes state.

Contribution of Selective Addressing: Reduction in Power Consumption

At each change of image, although all the TFTs of an addressed rowreceive a gate open signal simultaneously, only the pixels that have tochange state will receive a control signal, via the drain of theassociated TFT. In the case of the other pixels, that is to say thosefor which a change of state is not desired, the sources and drains ofthe associated TFTs will remain at zero potential. The power consumptionwill thus be markedly reduced, even to zero in the case of slowlyvarying images.

Contribution of the TFT: Isolation of the Pixel

The transistor coupled to each pixel acts as a switch, which is closedfor a short time (from about ten to a few tens of μs) when charging thedata, and which is open for the rest of the frame time. Eachliquid-crystal pixel is thus isolated from the other pixels and from thecolumn data that travel along the column tracks. No flicker effectappears when addressing an image, without any limit as regards thenumber of pixels addressed.

Contribution of the TFT: Increase in the Address Rate

The row address time for the active BiNem is, depending on the optionadopted, about 2 or 3 times the gate open time Tg, typically a few tensof μs, compared with the time needed for multiplexed addressing, whichis typically around 1 to 2 ms. Thus, an increase in accessible rate by afactor of about 50 is achieved with the active BiNem according to thepresent invention compared with passive multiplexing. As in the case ofstandard liquid crystals addressed by TFTs, addressing 1000 rows at avideo rate is therefore possible in active BiNem mode according to thepresent invention.

Contribution of the TFT: Better Propagation of Signals Along the Row

In a TFT screen, the signal is transported by very fine metal tracksbetween the pixels of width l_(p). Propagation along these rows takesplace according to the diffusion equation, as in the case of ITO tracks,but the surface resistance of these tracks is ≅0.1Ω, i.e. 100 timeslower. The diffusion time is thus reduced by a factor of one hundred forthe same screen. It arises only in the case of screens whose columns areten times longer.

The metal column track charges only one pixel at a time, but it isnarrower than the pixel. These effects partly compensate for each other.The conductivity of the metal allows the charging time due to theresistance of the track to be neglected. For a square screen of sizeL=85 mm, the pixels of which are square with sides of L/n, the ratio ofthe diffusion time T_(d) to the charging time T_(c) for a metal track ofwidth l_(p) is, for 400 square pixels with sides of 210 μm:

$\begin{matrix}{{T_{d}/T_{c}} = {\left( {R_{s{({ITO})}}/R_{s{({metal})}}} \right)\left( {n^{2}{1_{p}/L}} \right)}} \\{\cong {\left( {15/0.1} \right) \times \left( {400 \times 400 \times 5\mspace{14mu}{{\mu m}/85}\mspace{14mu}{mm}} \right)}} \\{= 1400.}\end{matrix}$

Thus, it may be seen that there is no limitation as regards deformationof the falling edges of the column signal by the R_(s) of the trackduring propagation along the column.

It is the resistance of the TFT in the on state that determines thecapability of voltage charging and discharging (EC and ES phases) in asufficiently short time.

Technological Aspect: Specification of the TFT

The above simulations show that the use of a standard TFT is compatiblewith the invention according to option 1 (application of address andcontrol signals during three successive phases spaced apart in time, Tg,Tg′ and Tg″) for binary switching between the U and T states.

The switching of the BiNem depends on the waveform of the signal appliedand particularly on the waveform of its falling edge. The value of theresistance R_(on) of the transistor must therefore allow a charging ordischarging time of less than 30 μs. This can be easily achieved with astandard mobility (cf. simulations). To increase the resolution and therate of an active BiNem screen according to the present invention, it ispossible to use a transistor that allows more rapid charging anddischarging of the pixel voltage so as to reduce the gate open times Tg,Tg′ and Tg″. This is achieved, for example, with a TFT of greatermobility μ₀ than that chosen for the simulation, or with a shortertransistor (shorter channel length), since R_(off) is not critical.

As regards the resistance R_(off) of the transistor, this is involved asit transmits, to a given pixel, the column signal from the other pixelsattenuated by the R_(off)C_(tx) filter. It should be pointed out thatthe constraint on R_(off) is in this case much less than in the case ofthe TFTs for conventional displays, since all that is required is forthe parasitic signal to be below the Fredericks voltage (0.5 V) so thatthere is no action on the pixel outside the switching times. During thebreaking time Tc, the constraint does not exist since all that isrequired is to increase P1 slightly in order for their to be no risk ofthis parasitic signal causing the voltage of the pixel to drop belowV_(c). It is therefore possible to use, for the two options (applicationof address and control signals of the three successive phases spacedapart in time Tg, Tg′ and Tg″ or application of the address and controlsignals over two successive phases spaced apart in time Tg and Tg′) a“degraded” transistor for which a lower R_(off) is tolerated, that is tosay one with greater leakage. In this case, some of the constraints onthe TFT parameters are lifted.

For the same reason, the tolerance on the resistivity of the liquidcrystal is greater than in the case of a TFT associated with a standardliquid-crystal effect. A lower liquid-crystal resistivity is permittedin the case of the active BiNem according to the present invention.

The use of addressing option 2 (two-transition addressing) recommends,for optimized operation, the addition of a discharge resistance R_(F) atthe terminals of the liquid crystal.

Conventionally, a storage capacitor C_(S) put into standard TFTs is usedto screen the interfering signal that would cause a variation in thevoltage at the terminals of the liquid crystal. Since the constraint onmaintaining the voltage is much less severe in the case of the activeBiNem according to the present invention, it is conceivable, in thedesign of an optimized TFT for a BiNem application, to reduce or eveneliminate this storage capacity C_(s).

The switch function fulfilled by the transistor may also be fulfilled bya system based on one or two diodes, as illustrated in FIGS. 23 and 24.The rows 46 and the columns 45 are each on one face of the cell(technology simplification). The columns 45 may be produced by aconventional ITO track on a first plate. The second plate includes ITOpads 47, placed opposite the columns 45 in order to define the pixels.Moreover, the second plate carries diodes 100 placed respectively, foreach pixel, between a row 46 and an associated pad 47. The direction ofeach diode 100 depends on the polarity of the signals applied betweenrows and columns. The diodes are positioned so as to operate “in reversemode”, that is to say to allow a signal current to flow when theyreceive a reverse voltage of greater than their Zener voltage V_(Z). Theabsolute value of this Zener voltage V_(Z) is chosen to be greater thanthe absolute value of P1.

For a positive voltage applied to the columns 45 and a negative voltageapplied to the rows 46, the diodes 100 have their anode on the row 46side and their cathode on the pads 47 side, and therefore on the column45 side.

With regard to FIG. 23:

-   -   to control the pixel defined at the intersection of row 1 (46)        and column 45, a voltage −V_(Z) is applied to the row 1 and a        positive voltage P1 is applied to the column 45. The        corresponding pixel sees a voltage P1 at its terminals because        of the voltage drop of absolute value V_(Z) at the terminals of        the diode 100;    -   the pixel defined at the intersection of row 2 (46) and the same        column 45 is not controlled. This is because, since row 2 is at        0 volts, the associated diode 100 sees a voltage P1 below its        Zener voltage V_(Z) and remains off.

The characteristic of the diode 100 is illustrated in FIG. 25.

A system based on two back-to-back diodes 100, 102, as illustrated inFIG. 24 (see the characteristic in FIG. 26), allows a similar operationwith a bipolar switching signal.

REFERENCES

-   Doc [1]: Patent FR 2 740 894;-   Doc [2]: PM Alt and P. Pleshko, IEEE Trans Electron Devices ED-21,    146-55, 1974;-   Doc [3]: Patent FR 0 204 940;-   Doc [4]: Patent FR 0 201 448;-   Doc [5]: C. Joubert, SID Proceedings, 2002, pages 30-33;-   Doc [6]: Patent FR 2 824 400.

The invention claimed is:
 1. Method for electrically controlling abistable nematic liquid crystal matrix screen composed of pixelsprovided in a matrix of rows and columns, comprising a liquid crystallayer between two substrates facing each other, two sets of electrodesplaced respectively on the substrates, each pixel having two electrodesforming respectively a drive pixel electrode and a back pixel electrode,the drive pixel electrode being connected to the crossing of one row andone column on one substrate, the back pixel electrode being provided onthe other substrate, an array of row conducting tracks and of columnconducting tracks, and an array of transistors respectively associatedwith each one of the pixels, said liquid crystal matrix screen includinga weak zenithal anchoring orientation layer on one of the substrates,each pixel of the bistable nematic liquid crystal matrix screen beingaddressed via a respective transistor, each transistor comprising agate, a source and a drain, each transistor being activated bysequentially scanning the row conducting tracks of the screen, the gateof each pixel transistor being connected to a respective row conductingtrack, the gate controlling the turning-off or turning on of thetransistor by applying address signal, the source of each pixeltransistor being connected to a respective column conducting track, thesource applying control signal, the drain being connected to the drivepixel electrode, said bistable nematic liquid crystal matrix screencomprising two bistable liquid crystal textures, one texture beinguniform or slightly twisted wherein the liquid crystal molecules beingat least approximately parallel to one another, and the other texturediffering from the first texture by a twist of about +180° or −180°,said electrically controlling consisting in switching each pixel betweenthe two bistable liquid crystal textures, the method comprisingsuccessively in time a first phase, an intermediate phase, and at leastone texture control phase, the first phase comprising: applying to thegate of the transistors of respective pixels corresponding to a commonrow, via said corresponding row conducting track, an address signal inorder to turn on the transistors of the common row, allowing the controlsignals applied to the source of the same transistors in synchronismwith the address signal to appear on the drain of said transistors andconsequently on the associated drive pixel electrodes, said controlsignals having a sufficient amplitude to permit breaking of theanchoring of the liquid crystal on said pixels, and then applying to thegate of the transistors of said common row, an address signal in orderto turn off the transistors, the intermediate phase having a controlledtime interval which is sufficient and adapted to break the anchoring ofthe liquid crystal of the said pixels and wherein several other rows areaddressed during said intermediate phase, the at least one texturecontrol phase comprising: applying again to the gate of the transistorsof said respective pixels corresponding to said common row, anadditional address signal in order to turn on again the transistorsallowing the control signals applied to the sources of said transistorsin synchronism with the address signal to appear on the drain of saidtransistors and consequently on the associated drive pixel electrodes,said control signals being applied in order to select the final bistableliquid crystal texture, then applying to the gate of the transistors ofsaid common row, an address signal in order to turn off the transistors.2. Method according to claim 1, wherein the steps of controllingswitching each pixel between the two bistable liquid crystal texturescomprise a sequence made up of a first phase and a single texturecontrol phase, the first phase and the texture control phase beingseparated by an intermediate phase.
 3. Method according to claim 1wherein a discharge resistor is provided respectively at the terminalsof each pixel.
 4. Method according to claim 1, wherein the steps ofcontrolling switching each pixel between the two bistable liquid crystaltextures comprise a sequence made up of a first phase and two texturecontrol phases, the first phase and the texture control phases beingseparated by two respective intermediate phases.
 5. Method according toclaim 4, wherein said sequence comprises: the first phase comprising:applying to the gate of the transistors of respective pixelscorresponding to a common row, via said corresponding row conductingtrack, an address signal in order to turn on the transistors of thecommon row, allowing the control signals applied to the source of thesame transistors in synchronism with the address signal to appear on thedrain of said transistors and consequently on the associated drive pixelelectrodes, said control signals having a sufficient amplitude to permitbreaking of the anchoring of the liquid crystal on said pixels, and thenapplying to the gate of the transistors of said common row, an addresssignal in order to turn off the transistors, a first intermediate phasehaving a controlled time interval which is sufficient and adapted tobreak the anchoring of the liquid crystal of the said pixels and whereinseveral other rows are addressed during said intermediate phase, a firsttexture control phase comprising: applying again to the gate of thetransistors of said respective pixels corresponding to said common row,an additional address signal in order to turn on again the transistorsallowing the control signals applied to the sources of said transistorsin synchronism with the address signal to appear on the drain of saidtransistors and consequently on the associated drive pixel electrodes,said control signals being applied in order to select the final bistableliquid crystal texture, then applying to the gate of the transistors ofsaid common row, an address signal in order to turn off the transistors,a second intermediate phase having a controlled time interval, a secondtexture control phase comprising: applying again to the gate of thetransistors of said respective pixels corresponding to said common row,an additional address signal in order to turn on again the transistorsallowing the control signals applied to the sources of said transistorsin synchronism with the address signal to appear on the drain of saidtransistors and consequently on the associated drive pixel electrodes,said control signals corresponding to a reset to zero signal, and thenapplying to the gate of the transistors of said common row, an addresssignal in order to turn off the transistors.
 6. Method according toclaim 4, wherein the select control signals applied during the firsttexture control phase is zero or small, in order to obtain a twistedtexture.
 7. Method according to claim 1, wherein the steps ofcontrolling switching each pixel between the two bistable liquid crystaltextures comprise a sequence made up of a first phase and more than twotexture control phases, the first phase and all the texture controlphases being separated by respective intermediate phases.
 8. Methodaccording to claim 1, wherein the control signals are of square-wavetype to obtain a twisted texture.
 9. Method according to claim 1,wherein the intermediate phase is designed to control the variation ofthe falling edge of each control signal, to obtain a uniform texture.10. Method according to claim 1, wherein the transistors have a degradedinternal resistance in the off state.
 11. Method according to claim 1,wherein the control signal is maintained at zero for the pixels whosestate does not have to be modified.
 12. Method according to claim 1,wherein the amplitude of control signals is adapted to obtain greylevels.
 13. Method according to claim 1, wherein the amplitude ofcontrol signals is adapted to obtain, after anchoring breaking, mixedtextures in which the two bistable textures coexist in a controlledproportion within one same pixel, these two textures being separated by180° disclination lines volumewise or by 180° reorientation walls on oneof the surfaces, and said method comprising the step of stabilization ofthe mixed textures by transformation of volume lines into surfaces wallsand the immobilization of these walls on the surface.